The present invention relates to forming components in semiconductor integrated circuits, and more specifically to forming metal-insulator-metal (MIM) capacitors.
In semiconductor integrated circuits (ICs or chips), a MIM capacitor may typically be formed as a planar capacitor patterned during a middle-of-line (MOL) process or back-end-of-line (BEOL) process. The term BEOL generally refers to the portion of integrated circuit fabrication during which interconnects are formed. However, the planar MIM capacitor can consume a significant amount of chip area in order to achieve a required amount of capacitance. Attempts have been made to increase the capacitance density by reducing the thickness of the dielectric layer formed between top and bottom metal electrodes and by using high dielectric constant materials. However, reducing the dielectric thickness can lead to undesired effects such as increased leakage currents. Additionally, the use of special dielectric materials may not be cost effective.